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integrated silicon solution, inc. 1-800-379-4774 1 advance information sr039-0b 05/14/99 this document contains advance information. issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 1999, integrated silico n solution, inc. features ? internal self-timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? pentium? or linear burst sequence control using mode input ? three chip enables for simple depth expansion and address pipelining ? common data inputs and data outputs ? jedec 100-pin tqfp and 119-pin pbga package ? single +3.3v +10%, C5% power supply ? 3.3v i/o supply ? power-down snooze mode description the issi is61sp25618 is a high-speed, low-power synchro- nous static ram designed to provide a burstable, high- performance, secondary cache for the pentium?, 680x0?, and powerpc? microprocessors. it is organized as 262,144 words by 18 bits, fabricated with issi 's advanced cmos technology. the device integrates a 2-bit burst counter, high- speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. bw1 controls dqa, bw2 controls dqb, conditioned by bwe being low. a low on gw input would cause all bytes to be written. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated inter- nally by the is61sp25618 and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. is61sp25618 256k x 18 synchronous pipelined static ram advance information may 1999 fast access time symbol parameter -166 -150 -133 -117 -5 units t kq clock access time 5 5555ns t kc cycle time 6 6.7 7.5 8.5 10 ns frenquency 166 150 133 117 100 mhz issi ?
is61sp25618 2 integrated silicon solution, inc. 1-800-379-4774 advance information sr039-0b 05/14/99 issi ? block diagram burst counter a a1 a0 gw mode adsc adsp address register dqa byte write register dqb byte write register enable register enable register bwe bw1 bw2 256k x 18 memory array 18 data input register clk 18 2 adv clk 2 18 18 16 2 clk2 data output register clk2 clk oe ce1 ce2 ce2 clr dqa - dqb
is61sp25618 integrated silicon solution, inc. 1-800-379-4774 3 advance information sr039-0b 05/14/99 issi ? pin configuration 119-pin pbga (top view) and 100-pin tqfp pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bw1 - bw2 synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2, ce2 synchronous chip enable oe output enable dq1-dq16 synchronous data input/output mode burst sequence mode selection v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v zz snooze enable gnd q isolated output buffer ground dqp1-dqp2 parity data i/o dqp1 is parity for dq1-8; dqp2 is parity for dq9-16 a17 nc nc vccq gnd nc dqp1 dq8 dq7 gnd vccq dq6 dq5 gnd nc vcc zz dq4 dq3 vccq gnd dq2 dq1 nc nc gnd vccq nc nc nc a6 a7 ce ce2 nc nc bw2 bw1 ce2 vcc gnd clk gw bwe oe adsc adsp adv a8 a9 nc nc nc vccq gnd nc nc dq9 dq10 gnd vccq dq11 dq12 nc vcc nc gnd dq13 dq14 vccq gnd dq15 dq16 dqp2 nc gnd vccq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a5 a4 a3 a2 a1 a0 nc nc gnd vcc nc nc a10 a11 a12 a13 a14 a15 a16 46 47 48 49 50 a b c d e f g h j k l m n p r t u vccq nc nc dq9 nc vccq nc dq12 vccq nc dq14 vccq dq16 nc nc nc vccq a6 ce2 a7 nc dq10 nc dq11 nc vcc dq13 nc dq15 nc dqp2 a5 a11 nc a4 a3 a2 gnd gnd gnd bw2 gnd nc gnd gnd gnd gnd gnd mode a10 nc adsp adsc vcc nc ce oe adv gw vcc clk nc bwe a1 a0 vcc nc nc a8 a9 a12 gnd gnd gnd gnd gnd nc gnd bw1 gnd gnd gnd gnd a14 nc a16 ce2 a15 dqp1 nc dq7 nc dq5 vcc nc dq3 nc dq2 nc a13 a17 nc vccq nc nc nc dq8 vccq dq6 nc vccq dq4 nc vccq nc dq1 nc zz vccq 1 2 3 4 5 6 7
is61sp25618 4 integrated silicon solution, inc. 1-800-379-4774 advance information sr039-0b 05/14/99 issi ? truth table address operation used ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write 2, 4 oe oe oe oe oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l xxxx high-z deselected, power-down none l l x l xxxx high-z deselected, power-down none x x h h l x x x high-z deselected, power-down none x 0 x h l x x x high-z read cycle, begin burst external l h l l x x x 5 x high-z read cycle, begin burst external l h l h 0 x read 5 x high-z write cycle, begin burst external l h l h l x write x high-z read cycle, continue burst next x x x h h l read l dq read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h x x x h l read l dq read cycle, continue burst next h x x x h l read h high-z write cycle, continue burst next x x x h h l write x high-z write cycle, continue burst next h x x x h l write x high-z read cycle, suspend burst current x x x h h h read l dq read cycle, suspend burst current x x x h h h read h high-z read cycle, suspend burst current h x x x h h read l dq read cycle, suspend burst current h x x x h h read h high-z write cycle, suspend burst current x x x h h h write x high-z write cycle, suspend burst current h x x x h h write x high-z partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bw1 bw1 bw1 bw1 bw1 bw2 bw2 bw2 bw2 bw2 read h h x x read h l h h write byte a h l l h write byte b h l h l write all bytes h l l l write all bytes l x x x notes: 1. x = don't care. 1 = logic low. 2. write is defined as either 1) any bwx and bwe low or 2) gw is low. 3. oe is an asynchronous signal and is not sampled by the clock clk. oe drives the bus immediately (t oelz ) following oe going low. 4. on write cycles that follow read cycles, oe must be negated prior to the start of the write cycle to ensure proper write data setup times. oe must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. this read assumes the ram was previously deselected.
is61sp25618 integrated silicon solution, inc. 1-800-379-4774 5 advance information sr039-0b 05/14/99 issi ? interleaved burst address table (mode = v ccq or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd q ) 0,0 1,0 0,1 a1', a0' = 1,1 absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias C40 to +85 c t stg storage temperature C55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins C0.5 to v ccq + 0.3 v v in voltage relative to gnd for C0.5 to v cc + 0.5 v for address and control inputs v cc voltage on vcc supply relatiive to gnd C0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up.
is61sp25618 6 integrated silicon solution, inc. 1-800-379-4774 advance information sr039-0b 05/14/99 issi ? operating range range ambient temperature v cc / v ccq commercial 0 c to +70 c 3.3v +10%, C5% industrial C40 c to +85 c 3.3v +10%, C5% dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = C4.0 ma, v ccq = 3.3v 2.4 v v ol output low voltage i ol = 8.0 ma, v ccq = 3.3v 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage C0.3 0.8 v i li input leakage current gnd v in v ccq (2) com. C2 2 m a ind. C5 5 i lo output leakage current gnd v out v ccq , oe = v ih com. C2 2 m a ind. C5 5 power supply characteristics (over operating range) -166 -150 -133 -117 -5 symbol parameter test conditions max. max. max. max. max. uni t i cc ac operating device selected, com. 200 190 180 170 160 ma supply current all inputs = v il or v ih ind. 200 190 180 170 oe = v ih , vcc = max. cycle time 3 t kc min. i sb standby current device deselected, com. 70 65 60 55 50 ma v cc = max., ind. 70 65 60 55 all inputs = v ih or v il clk cycle time 3 t kc min. i zz power-down mode zz = v ccq com. 55555ma current clock running ind. 15 15 15 15 all inputs gnd + 0.2v or 3 vcc C 0.2v note: 1. the mode pin has an internal pullup. this pin may be a no connect, tied to gnd, or tied to v ccq . 2. the mode pin should be tied to vcc or gnd. it exhibits 10 m a maximum leakage current when tied to gnd + 0.2v or 3 vcc C 0.2v.
is61sp25618 integrated silicon solution, inc. 1-800-379-4774 7 advance information sr039-0b 05/14/99 issi ? capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 5 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 3.3v. ac test conditions parameter unit input pulse level 0v to 3v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads figure 2 317 w 5 pf including jig and scope 351 w output 3.3v figure 1 output buffer z o = 50 w 1.5v 50 w 30 pf
is61sp25618 8 integrated silicon solution, inc. 1-800-379-4774 advance information sr039-0b 05/14/99 issi ? read/write cycle switching characteristics (over operating range) - 166 -150 -133 -117 -5 symbol parameter min. max. min. max. min. max. min. max. min. max. unit f max clock frequency 166 150 133 117 100 mhz t kc cycle time 6 6.7 7.5 8.5 10 ns t kh clock high time 2.4 2.6 2.8 3.4 4 ns t kl clock low time 2.4 2.6 2.8 3.4 4 ns t kq clock access time 5 5 5 5 5 ns t kqx (1) clock high to output invalid 1.5 1.7 1.9 1.5 2.5 ns t kqlz (1,2) clock high to output low-z 0 0 0 0 0 ns t kqhz (1,2) clock high to output high-z 1.3 6 1.5 6.7 1.5 7.5 1.5 8.5 1.5 10 ns t oeq output enable to output valid 3.5 3.5 3.8 4 5 ns t oeqx (1) output disable to output invalid 0 0 0 0 0 ns t oelz (1,2) output enable to output low-z 0 0 0 0 0 ns t oehz (1,2) output disable to output high-z 2 3.5 2 3.5 2 3.8 2 4.2 2 5 ns t as address setup time 1.5 1.5 1.5 1.5 1.5 ns t ss address status setup time 1.5 1.5 1.5 1.5 1.5 ns t ws write setup time 1.5 1.5 1.5 1.5 1.5 ns t ces chip enable setup time 1.5 1.5 1.5 1.5 1.5 ns t avs address advance setup time 1.5 1.5 1.5 1.5 1.5 ns t ah address hold time 0.5 0.5 0.5 0.5 0.5 ns t sh address status hold time 0.5 0.5 0.5 0.5 0.5 ns t wh write hold time 0.5 0.5 0.5 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 0.5 0.5 0.5 ns t avh address advance hold time 0.5 0.5 0.5 0.5 0.5 ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
is61sp25618 integrated silicon solution, inc. 1-800-379-4774 9 advance information sr039-0b 05/14/99 issi ? read/write cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bw4-bw1 bwe gw a16-a0 adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b
is61sp25618 10 integrated silicon solution, inc. 1-800-379-4774 advance information sr039-0b 05/14/99 issi ? write cycle switching characteristics (over operating range) - 166 -150 -133 -117 -5 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t kc cycle time 6 6.7 7.5 8.5 10 ns t kh clock high time 2.4 2.6 2.8 3.4 4 ns t kl clock low time 2.4 2.6 2.8 3.4 4 ns t ds data in setup time 2 2 2 2 2 ns t as address setup time 1.5 1.5 1.5 1.5 1.5 ns t ss address status setup time 1.5 1.5 1.5 1.5 1.5 ns t ws write setup time 1.5 1.5 1.5 1.5 1.5 ns t ces chip enable setup time 1.5 1.5 1.5 1.5 1.5 ns t avs address advance setup time 1.5 1.5 1.5 1.5 1.5 ns t ah address hold time 0.5 0.5 0.5 0.5 0.5 ns t sh address status hold time 0.5 0.5 0.5 0.5 0.5 ns t dh data in hold time 0.5 0.5 0.5 0.5 0.5 ns t wh write hold time 0.5 0.5 0.5 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 0.5 0.5 0.5 ns t avh address advance hold time 0.5 0.5 0.5 0.5 0.5 ns
is61sp25618 integrated silicon solution, inc. 1-800-379-4774 11 advance information sr039-0b 05/14/99 issi ? write cycle timing single write data out data in oe ce2 ce2 ce bw4-bw1 bwe gw a16-a0 adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
is61sp25618 12 integrated silicon solution, inc. 1-800-379-4774 advance information sr039-0b 05/14/99 issi ? snooze and recovery cycle switching characteristics (over operating range) - 166 -150 -133 -117 -5 symbol parameter min. max. min. max. min. max. min. max. min. max. unit t kc cycle time 6 6.7 7.5 8.5 10 ns t kh clock high time 2.4 2.6 2.8 3.4 4 ns t kl clock low time 2.4 2.6 2.8 3.4 4 ns t kq clock access time 5 5 5 5 5 ns t kqx (1) clock high to output invalid 1.5 1.7 1.9 1.5 2.5 ns t kqlz (1,2) clock high to output low-z 0 0 0 0 0 ns t kqhz (1,2) clock high to output high-z 1.3 3.6 1.5 6.7 1.5 7.5 1.5 8.5 1.5 10 ns t oeq output enable to output valid 3.5 3.5 3.9 4 5 ns t oeqx (1) output disable to output invalid 0 0 0 0 0 ns t oelz (1,2) output enable to output low-z 0 0 0 0 0 ns t oehz (1,2) output disable to output high-z 2 3.5 2 3.5 2 3.8 2 4.2 2 5 ns t as address setup time 1.5 1.5 1.5 1.5 1.5 ns t ss address status setup time 1.5 1.5 1.5 1.5 1.5 ns t ces chip enable setup time 1.5 1.5 1.5 1.5 1.5 ns t ah address hold time 0.5 0.5 0.5 0.5 0.5 ns t sh address status hold time 0.5 0.5 0.5 0.5 0.5 ns t ceh chip enable hold time 0.5 0.5 0.5 0.5 0.5 ns t zzs zz standby 2 2 2 2 2 cyc t zzrec zz recovery 2 2 2 2 2 cyc notes: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
is61sp25618 integrated silicon solution, inc. 1-800-379-4774 13 advance information sr039-0b 05/14/99 issi ? snooze and recovery cycle timing single read high-z high-z data out data in zz oe ce2 ce2 ce bw4-bw1 bwe gw a16-a0 adv adsc adsp clk rd1 1a read snooze with data retention t kc t kl t kh t ss t sh t as t ah rd2 t ces t ceh t ces t ceh t ces t ceh t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz t zzs t zzrec
is61sp25618 14 integrated silicon solution, inc. 1-800-379-4774 advance information sr039-0b 05/14/99 issi ? ordering information commercial range: 0 c to +70 c frequency order part number package 166 is61sp25618-166tq tqfp is61sp25618-166b pbga 150 is61sp25618-150tq tqfp is61sp25618-150b pbga 133 is61sp25618-133tq tqfp is61sp25618-133b pbga 117 IS61SP25618-117TQ tqfp is61sp25618-117b pbga 100 is61sp25618-5tq tqfp is61sp25618-5b pbga industrial range: C40 c to +85 c frequency order part number package 150 is61sp25618-150tqi tqfp 133 is61sp25618-133tqi tqfp 117 IS61SP25618-117TQi tqfp 100 is61sp25618-5tqi tqfp issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com

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